Hi Mikemoy,
With the latest libmraa, Version: v0.5.2-37-g148c22f, you should be able to get up to 4 bytes without any CS toggle in between.
When I set 25MHz for SPI, "mraa_spi_frequency(spi,25000000);"
I measure SCLK is only 6.5MHz on my scope. ( As reference the OSC out measures correctly at 19.2 MHz)
The Intel® Edison Compute Module Hardware Guide says:
4.4 SPI interface
An SPI interface is available on pins 51, 53, 55, 57, and 59. The interface has two available chip selects.
• In a single-frame transfer, the SoC supports all four possible combinations for the serial clock phase and polarity.
• In multiple frame transfer, the SoC supports SPH=1 and SPO= 0 or 1.
• The SoC may toggle the slave select signal between each data frame for SPH=0.
• 25 MHz Master mode, 16.67 MHz slave mode.
Which clock is 25MHz? The edison internal clock ? or output SCLK ?
Can anyone please confirm if SCLK is supposed to be 25MHz?