All,,
The main requirement for supporting 4K@60 on DP SST (single-stream transport) is that the core display clock (CDCLK), which is configured by SBIOS, must be set high enough to drive the dot clock required by the mode. Usually 4K@60 has a 536MHz dot clock, so it requires a 540MHz CDCLK. If the system OEM did not configure the CDCLK at 540MHz for thermal, power saving, or other reasons, then the system will not be able to drive 4K@60 over a single DP stream.
This shouldn’t affect DP MST tiled displays because for those we use two streams, each for one half of the display, reducing the pixel clock.
Additionally, 4K support is only available on the Core processor graphics. Celeron and Pentium do not support 4K. All Core Haswell processors will support HBR2 with the exception of Haswell ULX.
Here is a reference guide that can be of help.
Excerpt from above:
| Processor | 4th generation Intel® Core™ processor family (Intel® Iris™ Pro Graphics 5200 / Intel® Iris™ Graphics 5100, Intel® HD Graphics 5000 / 4600 / 4400 / 4200) | 3rd generation Intel® Core™ processor family (Intel® HD Graphics 4000 / 2500) |
|---|---|---|
FEATURE | BENEFIT | |
Maximum Display Resolution | Higher pixel resolutions allow the PC to show more image detail. | DisplayPort* 1.2 / eDP* |